Performance Aspects of Gate Matrix Layout
نویسندگان
چکیده
This paper introduces performance aspects as a new optimization criteria when generating Gate Matrix Layouts. A new layout model is presented that limits the amount o f parasitic capacitance in signal paths and the resistance in power supply lines. The performance considerations are combined with a new layout s-trate g y that improves circuit performance with little or no area penalty. A n Automatic Transistor Layout Synthesizer (ATLAS) implements the proposed changes t o the Gate Matrix Layout style.
منابع مشابه
Performance Aspects of Gate Matrix Layout - VLSI Design, 1993. Proceedings. The Sixth International Conference on
This paper introduces performance aspects as a new optimization criteria when generating Gate Matrix Layouts. A new layout model is presented that limits the amount o f parasitic capacitance in signal paths and the resistance in power supply lines. The performance considerations are combined with a new layout s-trate g y that improves circuit performance with little or no area penalty. A n Auto...
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